A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a CMOS imager 100 having a pixel array 102 connected to column sample and hold (S/H) circuitry 136. The pixel array 102 comprises a plurality of pixels 110 arranged in a predetermined number of rows and columns. The illustrated pixel 110 contains a pinned photodiode photosensor 112, transfer gate 114, a floating diffusion region FD to collect charge transferred from the photosensor 112, a reset transistor 116, row select transistor 120 and a source follower output transistor 118. The pixel 110 also includes a storage gate 124 for storing charge from the photosensor 112 in a channel region 124b when a storage gate control signal SG is applied to a storage gate control line 124a. FIG. 1 also shows an anti-blooming gate 125, which may be used to drain away excess charge from the photosensor 112 to region 127 when an anti-blooming control signal AB is applied to the anti-blooming gate 125. Without the anti-blooming gate 125, the pixel 110 is a five transistor (5T) pixel. If the anti-blooming gate 125 is used, the pixel 110 is a six transistor (6T) pixel.
The reset transistor 116 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa-pix. A reset control signal RST is used to activate the reset transistor 116, which resets the floating diffusion region FD to the array pixel supply voltage Vaa-pix level as is known in the art. The source follower transistor 118 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa-pix and the row select transistor 120. The source follower transistor 118 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 120 is controllable by a row select signal SEL for selectively connecting the source follower transistor 118 and its output voltage signal Vout to a column line 122 of the pixel array 102.
In operation, the pixels 110 of each row in the array 102 are all turned on at the same time by a row select line e.g., SEL(0) and the pixels 110 of each column are selectively output onto a column line 122. A plurality of row and column lines are provided for the entire array 102. The row lines e.g., SEL(0) are selectively activated by row decoder 130 and driver circuitry 132 in response to an applied row address. Column select lines (not shown) are selectively activated in response to an applied column address by column circuitry that includes column decoder 134. Thus, row and column addresses are provided for each pixel 110. The CMOS imager 100 is operated by a sensor control and image processing circuit 150, which controls the row and column circuitry for selecting the appropriate row and column lines for pixel readout.
Each column is connected to sampling capacitors and switches in the S/H circuitry 136. A pixel reset signal Vrst and a pixel image signal Vsig for selected pixels are sampled and held by the S/H circuitry 136. A differential signal (Vrst-Vsig) is produced for each readout pixel by the differential amplifier 138 (AMP), which applies a gain to the signal received from the S/H circuitry 136. The differential signal is digitized by an analog-to-digital converter 140 (ADC). The analog-to-digital converter 140 supplies the digitized pixel signals to the sensor control and image processing circuit 150, which among other things, forms a digital image output. The imager also contains biasing/voltage reference circuitry 144.
The FIG. 1 imager 100 has a pixel configuration that uses a storage gate 124 and anti-blooming gate 125 to achieve a global shutter operation (as opposed to a rolling shutter). Typically, the TX, RST, SG, and SEL control signals are driven horizontally from the row driver 132 (respectively shown as TX(0), RST(0), SG(0) and SEL(0) to indicate signals for row number 0 in the array 102) while the pixel power (e.g., Vaa-pix) and output Vout are routed vertically to the column circuitry 136.
There is a need and desire for an improved technique for achieving high dynamic range that does not suffer from the aforementioned shortcomings of the conventional techniques.